$STM $WOLF $NVTS $ON EXECUTIVE OVERVIEW The source table is a useful high-level competitive map of 650V-class GaN and SiC discretes, but it should not be treated as a clean device-ranking table. The central conclusion is that the market is not converging around a single superior device family. It is segmenting by power architecture, switching topology, thermal path, packaging, qualification status, and customer-specific reference design adoption. At 650V and 400V operating assumptions, SiC retains a measurable conduction-loss and ruggedness advantage in high-current, lower-frequency, thermally constrained stages, while GaN retains the structural advantage in high-frequency, low-output-charge, low-reverse-recovery designs where magnetics reduction, power density, and switching-loss minimization dominate. The investable implication is that device-level Rds_on is necessary but insufficient; the durable competitive advantages will accrue to vendors that can deliver full system-level power conversion platforms with qualified packages, credible thermal paths, drivers or control ICs, reference designs, field reliability data, and supply assurance. The table’s most important message is not that GaN is “better” than SiC or vice versa. The most important message is that 650V-class power semiconductors are moving from a device-specification competition into a system-architecture competition. AI server power, telecom power, PV, EV charging, UPS, and BESS applications are all pulling wide-bandgap devices into higher-volume use cases, but the winning socket depends on whether the customer is optimizing for a 400V bus, 48V/54V rack power, 800V HVDC distribution, totem-pole PFC, LLC, matrix conversion, or isolated bus conversion. NVIDIA’s 800 VDC architecture is especially important because it shifts the debate away from a pure 650V discrete comparison and toward higher-voltage, fewer-stage, system-level power conversion. NVIDIA states that 800 VDC reduces conversion stages, current, copper, cable bulk, and data center distribution losses versus 54 VDC rack-level systems and 480 VAC facility-level systems, and lists many of the table’s vendors among its ecosystem partners.  SOURCE MATERIAL AND DATA QUALITY The table normalizes around 650V-class SiC and GaN devices, with values stated at 80C and Coss/Eoss/Qoss-style metrics assumed at Vds = 400V. That is a reasonable first-order benchmark for 400V DC-link server PSU and PFC contexts, but it creates several comparability problems. First, the table mixes 650V and 700V devices. Second, it mixes discrete FETs, integrated-driver GaN devices, cascode GaN, e-mode GaN, SiC MOSFETs, and highly integrated offline power ICs. Third, it mixes TOLT, TOLL, TO-247, TO-263, BHDFN, QFN, and other package formats. Fourth, several cells are missing, marked with “?”, or subjectively annotated as “wrong package,” “in development,” “no charts,” or “website confusing.” Fifth, power dissipation is especially difficult to compare because datasheet power dissipation depends heavily on whether the measurement assumes case, ambient, board, top-side cooling, bottom-side cooling, thermal pad, cold plate, or package-only limits. The table is therefore most useful as a screening framework, not as a procurement-grade ranking. The “wrong package” notation is best interpreted as a package-normalization critique rather than a technology critique. A TOLL or TO-247 device is not wrong in an absolute sense; it is wrong only if the benchmark objective is a top-side-cooled, low-inductance, high-power-density device suitable for compact AI server PSU mechanics. TO-247 remains relevant in industrial, EV charging, lab, and lower-density applications. TOLL is highly relevant for bottom-side-cooled SMD designs. TOLT is strategically important where top-side heat extraction to a cold plate, airflow channel, or lid is desired while reducing PCB thermal stress. The table implicitly favors top-side-cooled high-density architectures, which is directionally aligned with AI power density trends, but that bias should be recognized. TECHNOLOGY INTERPRETATION The core device trade-off is clear. The SiC rows generally show lower Rds_on at comparable voltage class and higher apparent thermal current capability. The best SiC entries in the table sit around 13mΩ to 21mΩ, while most GaN entries sit around 25mΩ to 42mΩ. Since conduction loss scales with I²R, a 42mΩ device has 68% higher conduction loss than a 25mΩ device at the same current before thermal and temperature-coefficient effects are considered. At 50A, a 25mΩ device dissipates 62.5W from conduction alone, while a 42mΩ device dissipates 105W. This difference matters in high-current PFC legs, hard-worked primary switches, and applications where thermal headroom is the binding constraint. GaN’s advantage is in the dynamic loss domain. The GaN devices in the table typically show materially lower capacitance and stored-energy figures than many SiC alternatives, with lower Eoss and Qoss values for several GaN entries. This is critical for high-frequency switching and resonant or quasi-resonant topologies because the system-level benefit is not only lower transistor loss; it is also smaller magnetics, smaller capacitors, lower mechanical volume, and potentially fewer conversion stages. Zero reverse-recovery charge is a key GaN benefit in totem-pole PFC and high-frequency half-bridge designs. Infineon’s 650V CoolGaN page highlights ultrafast switching, no reverse-recovery charge, low output charge, low gate charge, top-side cooling, and applications including data center power, telecom AC-DC conversion, EV charging, PV, and industrial power supplies.  The practical conclusion is that SiC is favored when conduction, thermal robustness, avalanche behavior, high voltage, and rugged field use dominate, while GaN is favored when switching frequency, power density, reverse-recovery elimination, and passive-component shrinkage dominate. In server PSUs, both can win different stages. Infineon explicitly frames single-phase and three-phase server PSUs as hybrid Si, SiC, and GaN systems, with SiC and Si commonly suited to single-phase PFC, SiC and GaN suited to three-phase PFC, and SiC or GaN suited to DC-DC LLC stages. Infineon also describes AI rack power moving from roughly 100kW toward 1MW+ per rack and references benchmark PSU efficiency near 98%.  INFINEON Infineon appears to have one of the strongest combined positions in the source table because it has credible 650V-class offerings on both sides of the SiC/GaN divide. The IGLT65R025D2 row shows a TOLT GaN device with 650V rating, 35mΩ Rds_on at the table’s 80C condition, 105pF Coss, 800pF Ciss, 12µJ Eoss, and 82nC Qoss. The IMLT65R015M2H row shows a TOLT SiC device with 17.5mΩ Rds_on, 200pF Coss, 3000pF Ciss, 20µJ Eoss, and 150nC Qoss. In simple terms, Infineon’s SiC entry looks materially stronger on conduction and thermal capability, while its GaN entry looks materially stronger on stored energy and input capacitance. That is exactly the kind of dual-platform optionality that matters when customer architectures remain fluid. Infineon’s strategic advantage is not merely the device pair. It is the combination of CoolGaN, CoolSiC, drivers, controllers, reference designs, application engineering, and data center power positioning. The company’s 650V SiC product page identifies CoolSiC discretes for server SMPS, ESS, solar inverters, EV charging, UPS, and industrial SMPS, while its data-center page explicitly positions Infineon from grid to core across Si, SiC, GaN switches, gate drivers, power stages, sensors, controllers, and MCUs.  The investment implication is that Infineon is better positioned as a broad platform beneficiary than as a single-device winner. The trade-off is that AI power upside is diluted across a large diversified semiconductor base, and device-level leadership in any one row does not automatically translate into disproportionate equity upside. NAVITAS Navitas is one of the highest-beta pure-play exposures in the table because it has both GaN and SiC entries and is highly aligned with AI data center power narratives. The NV6524 row shows a 650V TOLT GaN device with integrated driver, 25mΩ Rds_on, 240W max power dissipation in the table, 150pF Coss, 16µJ Eoss, and 125nC Qoss. That combination is attractive because 25mΩ is among the lower GaN Rds_on values in the table, while integrated drive and protection can reduce adoption friction. Navitas’ own NV6524 datasheet describes a 650V continuous / 800V transient GaNSafe top-cooled TOLT device, 25mΩ max Rds_on at 25C, 90A continuous current, zero reverse-recovery charge, dV/dt programmability, operation up to 2MHz, short-circuit protection with 350ns latency, and 100V/ns dV/dt immunity.  The source table’s Navitas SiC entry is flagged as “wrong package,” which reduces its comparability to top-side-cooled GaN devices, but the strategic point is that Navitas is attempting to bundle GaN and SiC into AI power reference platforms. Navitas has promoted 4.5kW and 8.5kW AI data-center power reference designs using GaNSafe and Gen-3 Fast SiC, claiming over 97% efficiency and 137W/in³ for the 4.5kW design, and approximately 98% efficiency for an 8.5kW OCP/ORv3-oriented solution.  The key investment question is execution rather than technology concept. A pure-play GaN/SiC company can have substantial upside if AI power designs convert into production revenue, but it also carries higher customer-concentration, qualification-timing, balance-sheet, and valuation risk than diversified analog and power incumbents. RENESAS Renesas is strategically important because the Transphorm acquisition gave it a credible high-voltage GaN platform with a silicon-compatible cascode architecture. The source table lists TP65H030G4PRS as a TOLT GaN device with 650V rating, 42mΩ Rds_on at the table condition, 140pF Coss, 1800pF Ciss, 15µJ Eoss, and 135nC Qoss. Official product information states that TP65H030G4PRS is an active 650V, 30mΩ SuperGaN FET in TOLT, with 41mΩ max Rds_on, 135nC Qoss, 127pF Coss, 1500pF Ciss, standard gate-drive compatibility, dynamic Rds_on production testing, and applications including AI datacenter and telecom power supplies, e-mobility charging, PV inverter, UPS, and BESS.  Renesas’ differentiation is ease of adoption and field experience. The company describes its Gen IV Plus GaN FETs as available in TOLT, TO-247, and TOLL, aimed at AI data centers, server power systems, 800V HVDC architecture, e-mobility charging, UPS, BESS, and solar inverters. It also states that the platform uses a d-mode normally-off architecture with a low-voltage silicon MOSFET input stage, standard off-the-shelf gate driver compatibility, more than 20M GaN devices shipped, and more than 300B field hours.  The caveat is that Renesas does not screen as a full SiC/GaN dual leader in this table. Its strength is GaN plus analog/control/system integration, not broad 650V SiC parity with Infineon or ST. STMICROELECTRONICS ST has a credible SiC position and an emerging GaN position, but the timing of the GaN product matters. The source table lists SGT023R70FTP as a 700V TOLT GaN device with a tentative 30mΩ Rds_on, 200W to 250W power dissipation, 233pF Coss, 218pF Ciss, unknown Eoss, and 190nC Qoss, with the comment “In development.” ST’s product page confirms that SGT023R70FTP is a 700V, 18mΩ typical e-mode PowerGaN transistor in preview/design stage, with no distributor availability reported in the page view.  This is an important correction to the table: ST’s GaN entry may be technically interesting, but it should not be weighted equally with fully available production parts. ST’s 650V SiC entry is much more mature. The table lists SCT014TO65G3 as a TOLL SiC device with 14mΩ Rds_on, 400W power dissipation, 250pF Coss, and 3000pF Ciss. ST’s official page describes SCT014TO65G3 as an active, volume-production 650V, 13.5mΩ typical, 110A SiC MOSFET in a TO-LL package, developed using 3rd-generation SiC technology, with low Rds_on across temperature, low capacitances, high-speed switching, and a source-sensing pin.  The conclusion is that ST is a stronger current SiC incumbent than a current 650V GaN production leader in this specific table, although its GaN roadmap remains strategically relevant. ONSEMI Onsemi’s table position is strong in SiC and optional in GaN. The source table lists NVBG015N065SC1 as a 650V SiC device with 13mΩ Rds_on, 250W power dissipation, 400pF Coss, and 4000pF Ciss, but flags the package as wrong. Official onsemi data describes NVBG015N065SC1 as a 650V SiC MOSFET in D2PAK-7L with 12mΩ typical Rds_on at 18V gate drive and 15mΩ typical at 15V, low effective Coss, 100% avalanche testing, and AEC-Q101 qualification.  This is a credible rugged SiC part, but it is not a clean TOLT benchmark device. The more strategically interesting issue is Onsemi’s vertical GaN roadmap. The table characterizes vertical GaN as potentially “amazing if it works,” but currently “hopes and dreams.” That is directionally fair as a production-screen comment, but it should be updated for 2025-2026 developments. Onsemi announced vertical GaN built on GaN-on-GaN technology, claimed almost 50% lower losses, cited more than 130 patents, and stated that it is sampling 700V and 1200V devices to early access customers.  Separately, onsemi announced a collaboration with GlobalFoundries to develop high-performance 650V lateral GaN-on-silicon solutions for AI data centers, automotive, aerospace, and other markets.  Onsemi therefore has credible optionality, but the investment case remains roadmap-heavy relative to Infineon, Renesas, Navitas, and existing production GaN vendors. WOLFSPEED Wolfspeed is a SiC specialist in this framework. The table correctly notes no GaN offering and lists C4MV015065T as a 650V TOLT SiC device with 17mΩ Rds_on, 125W power dissipation, 200pF Coss, 5000pF Ciss, and 28µJ Eoss. Official Wolfspeed product information identifies C4MV015065T as a 650V, 15mΩ, 150A, 175C, industrial-qualified Gen 4 SiC MOSFET in a TOLT top-side-cooled package.  The technology conclusion is that Wolfspeed’s device should be taken seriously where SiC ruggedness, top-side cooling, and high-current capability are priorities. The portfolio conclusion is more limiting: no GaN means Wolfspeed is less advantaged in system architectures where GaN wins the high-frequency switching socket. Wolfspeed is therefore more exposed to whether customers choose SiC-heavy or hybrid SiC/GaN architectures, rather than to a pure GaN inflection.
$STM
first mention in our archive Mar 7, 2026 · latest 1w ago
Mention stats
12
Mentions (12mo)
↑ 167%
30d (8 vs 3)
5
Voices mentioning
↑ 0%
30d (3 vs 3)
Price · Mention timeline
12 mentions since Mar 2026Loading price chart…